Currently, to calculate delay associated with an integrated circuit, a delay calculation tool is used. The delay calculation tool reads in a netlist and obtains the characterized timing and power information from a compiled file, and then creates a Standard Delay Format (SDF) file based on the loading and interconnect information for the netlist.
The compiled file basically stores all characterization data for a single standard cell, and is basically a complied version of another file (a “tech file”) which is the ASCII human readable format that has the timing/power information. For memories, the delay calculation tool creates a file (i.e. an annotate.v file) that has most of the timing information, and this file is created again based on the characterization information in the tech file specific to a memory type.
When performing Static Timing Analysis (STA) on the netlist using, for example, Synopsys PrimeTime, one would need the SDF file created by the delay calculation tool and also the timing information in Synopsys proprietary format (.lib files). In other words, both SDF files and .lib files (such as Synopsys proprietary files) are required.
Currently, there is no single source (repository) for timing/power information accessible to a multitude of 3rd part tools without the hassle of having to support multiple or vendor specific formats to store/represent this information. There is no architecture currently available to streamline and accurately represent all information that is specific to a given set of the technologies. There is no standardized view that accurately represents timing, power and functional information for a third party tool.